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HFA1113/883
July 1994
Output Limiting, Ultra High Speed Programmable Gain, Buffer Amplifier
Description
The HFA1113/883 is a closed loop buffer featuring a high degree of gain accuracy, wide bandwidth, low distortion, and programmable output limiting. This buffer is the ideal choice for high frequency applications requiring output limiting, especially those needing ultra fast overdrive recovery times. The output limiting function allows the designer to set the maximum positive and negative output levels, thereby protecting later stages from damage or input saturation. The sub-nanosecond overdrive recovery time quickly returns the amplifier to linear operation following an overdrive condition. Component and composite video systems will also benefit from this buffer's performance, as indicated by the excellent gain flatness, and 0.02%/0.04 Deg. Differential Gain/Phase specifications (RL = 150). A unique feature of the pinout allows the user to select a voltage gain of +1, -1, or +2, without the use of any external components, as described in the "Design Information" section. Compatibility with existing op amp pinouts provides flexibility to upgrade low gain amplifiers, while decreasing component count. Unlike most buffers, the standard pinout provides an upgrade path should a higher closed loop gain be needed at a future date. This amplifier is available without output limiting as the HFA1112/883. For applications requiring a standard buffer pinout, please refer to the HFA1110/883 datasheet.
Features
* This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * User Programmable Output Voltage Limiting * User Programmable For Closed-Loop Gains of +1, -1 or +2 Without Use of External Resistors * Low Differential Gain and Phase . . . . 0.02%/0.04 Deg. * Low Distortion (HD3, 30MHz) . . . . . . . . . . -73dBc (Typ) * Wide -3dB Bandwidth . . . . . . . . . . . . . . . 850MHz (Typ) * Very High Slew Rate . . . . . . . . . . . . . . . 2400V/s (Typ) * Fast Settling (0.1%) . . . . . . . . . . . . . . . . . . . . 13ns (Typ) * Excellent Gain Flatness (to 100MHz) . . . . 0.07dB (Typ) * Excellent Gain Accuracy . . . . . . . . . . . . . . 0.99V/V (Typ) * High Output Current . . . . . . . . . . . . . . . . . . 60mA (Typ) * Fast Overdrive Recovery. . . . . . . . . . . . . . . . <1ns (Typ)
Applications
* Video Switching and Routing * Pulse and Video Amplifiers * Wideband Amplifiers * RF/IF Signal Processing * Flash A/D Driver * Medical Imaging Systems
Ordering Information
PART NUMBER HFA1113MJ/883 HFA1113ML/883 TEMPERATURE RANGE -55oC -55oC to to +125oC +125oC PACKAGE 8 Lead CerDIP 20 Lead Ceramic LCC
Pinouts
HFA1113/883 (CERDIP) TOP VIEW
NC -IN +IN V1 300 2 3 4 + 300 8 7 6 5 VH V+ OUT VL NC 4 -IN 5 NC 6 +IN 7 NC 8 9 10 11 12 13 NC NC NC VVL 300 +
HFA1113/883 (CLCC) TOP VIEW
NC NC NC NC NC 18 VH 17 V+ 16 NC 15 OUT 14 NC
3
2
1 20 19 300
-
-
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
Spec Number
3-189
511106-883 File Number 3618.1
Specifications HFA1113/883
Absolute Maximum Ratings
Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Voltage at Either Input Terminal . . . . . . . . . . . . . . . . . . . . . . V+ to VVoltage at VH or VL Terminal . . . . . . . . . . . . . .(V+) + 2V to (V-) - 2V Output Current (50% Duty Cycle) . . . . . . . . . . . . . . . . . . . . . . . .55mA Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC ESD Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . < 2000V Storage Temperature Range . . . . . . . . . . . . . . -65oC TA +150oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC
Thermal Information
Thermal Resistance JA JC CerDIP Package . . . . . . . . . . . . . . . . . 115oC/W 30oC/W Ceramic LCC Package . . . . . . . . . . . . 75oC/W 23oC/W Maximum Package Power Dissipation at +75oC CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.87W Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.33W Package Power Dissipation Derating Factor above +75oC CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7mW/oC Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . 13.3mW/oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Supply Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Operating Temperature Range . . . . . . . . . . . . .-55oC TA +125oC RL 50
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at: VSUPPLY = 5V, RSOURCE = 0, RL = 100, VOUT = 0V, Unless Otherwise Specified. GROUP A SUBGROUPS 1 2, 3 Power Supply Rejection Ratio PSRRP VSUPPLY = 1.25V, V+ = 6.25V, V- = -5V, V+ = 3.75V, V- = -5V VSUPPLY = 1.25V, V+ = 5V, V- = -6.25V, V+ = 5V, V- = -3.75V VCM = 0V VCM = 2V, V+ = 3V, V- = -7V, V+ = 7V, V- = -3V Note 1 1 2, 3 1 2, 3 1 2, 3 CMSIBP 1 2, 3 1 2, 3 Gain (VOUT = 2VP-P) Gain (VOUT = 2VP-P) Gain (VOUT = 4VP-P) Output Voltage Swing AVP1 AVM1 AVP2 VOP100 VON100 Output Voltage Swing VOP50 VON50 Output Current +IOUT -IOUT AV = +1, VIN = -1V to +1V AV = -1, VIN = -1V to +1V AV = +2, VIN = -1V to +1V AV = -1 RL = 100 AV = -1 RL = 100 AV = -1 RL = 50 AV = -1 RL = 50 Note 2 VIN = -3.2V VIN = -2.7V VIN = +3.2V VIN = +2.7V VIN = -2.7V VIN = -2.25V VIN = +2.7V VIN =+2.25V 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1, 2 3 1, 2 3 1, 2 3 Note 2 1, 2 3 LIMITS TEMPERATURE +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC MIN -25 -40 39 35 39 35 -40 -65 25 20 0.980 0.975 0.980 0.975 1.960 1.950 3 2.5 2.5 1.5 50 30 MAX 25 40 40 65 40 50 1.020 1.025 1.020 1.025 2.040 2.050 -3 -2.5 -2.5 -1.5 -50 -30 UNITS mV mV dB dB dB dB A A A/V A/V k k V/V V/V V/V V/V V/V V/V V V V V V V V V mA mA mA mA
PARAMETERS Output Offset Voltage
SYMBOL VOS
CONDITIONS VCM = 0V
PSRRN
Non-Inverting Input (+IN) Current +IN Common Mode Rejection +IN Resistance
IBSP
+25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, +125oC, +125oC, -55oC -55oC -55oC +25oC +25oC +25oC +125oC, -55oC +25oC, +125oC -55oC +25oC, +125oC -55oC +25oC, +25oC, +125oC +125oC -55oC -55oC
+RIN
Spec Number 3-190
511106-883
Specifications HFA1113/883
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device Tested at: VSUPPLY = 5V, RSOURCE = 0, RL = 100, VOUT = 0V, Unless Otherwise Specified. GROUP A SUBGROUPS 1 2, 3 IEE Limiting Accuracy VHCLMP VLCLMP VH or VL Input Current VHBIAS VLBIAS NOTES: 1. Guaranteed from +IN Common Mode Rejection Test, by: +RIN = 1/CMSIBP . 2. Guaranteed from VOUT Test with RL = 50, by: IOUT = VOUT/50. RL = 100 AV = -1, VIN = -1.6V, VH = 1V AV = -1, VIN = +1.6V, VL = -1V VH = 1V VL = -1V 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 LIMITS TEMPERATURE +25oC +125oC, +125oC, +125oC, -55oC -55oC -55oC +25oC +25oC +25oC +125oC, -55oC +25oC +125oC, +125oC, -55oC -55oC +25oC MIN 14 -26 -33 -150 -200 -150 -200 -200 -300 MAX 26 33 -14 150 200 150 200 200 300 UNITS mA mA mA mA mV mV mV mV A A A A
PARAMETERS Quiescent Power Supply Current
SYMBOL ICC
CONDITIONS RL = 100
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS Table 2 Intentionally Left Blank.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS Device Characterized at: VSUPPLY = 5V, RL = 100, Unless Otherwise Specified. LIMITS PARAMETERS -3dB Bandwidth SYMBOL BW(-1) BW(+1) BW(+2) Gain Flatness GF30 GF50 GF100 Slew Rate +SR(-1) -SR(-1) +SR(+1) -SR(+1) +SR(+2) -SR(+2) CONDITIONS AV = -1, VOUT = 200mVP-P AV = +1, VOUT = 200mVP-P AV = +2, VOUT = 200mVP-P AV = +2, f 30MHz, VOUT = 200mVP-P AV = +2, f 50MHz, VOUT = 200mVP-P AV = +2, f 100MHz, VOUT = 200mVP-P AV = -1, VOUT = 5VP-P AV = -1, VOUT = 5VP-P AV = +1, VOUT = 5VP-P AV = +1, VOUT = 5VP-P AV = +2, VOUT = 5VP-P AV = +2, VOUT = 5VP-P NOTES 1 1 1 1 1 1 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC MIN 450 500 350 1500 1800 900 800 1200 1100 MAX 0.04 0.08 0.22 UNITS MHz MHz MHz dB dB dB V/s V/s V/s V/s V/s V/s
Spec Number 3-191
511106-883
Specifications HFA1113/883
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device Characterized at: VSUPPLY = 5V, RL = 100, Unless Otherwise Specified. LIMITS PARAMETERS Rise and Fall Time SYMBOL TR(-1) TF(-1) TR(+1) TF(+1) TR(+2) TF(+2) Overshoot +OS(-1) -OS(-1) +OS(+1) -OS(+1) +OS(+2) -OS(+2) Settling Time TS(0.1) TS(0.05) 2nd Harmonic Distortion HD2(30) HD2(50) HD2(100) 3rd Harmonic Distortion HD3(30) HD3(50) HD3(100) NOTES: 1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon data from multiple production runs which reflect lot-to-lot and within lot variation. 2. Measured between 10% and 90% points. 3. For 200ps input transition times. Overshoot decreases as input transition times increase, especially for AV = +1. Please refer to Performance Curves. CONDITIONS AV = -1, VOUT = 0.5VP-P AV = -1, VOUT = 0.5VP-P AV = +1, VOUT = 0.5VP-P AV = +1, VOUT = 0.5VP-P AV = +2, VOUT = 0.5VP-P AV = +2, VOUT = 0.5VP-P AV = -1, VOUT = 0.5VP-P AV = -1, VOUT = 0.5VP-P AV = +1, VOUT = 0.5VP-P AV = +1, VOUT = 0.5VP-P AV = +2, VOUT = 0.5VP-P AV = +2, VOUT = 0.5VP-P AV = +2, to 0.1%, VOUT = 2V to 0V AV = +2, to 0.05%, VOUT = 2V to 0V AV = +2, f = 30MHz, VOUT = 2VP-P AV = +2, f = 50MHz, VOUT = 2VP-P AV = +2, f = 100MHz, VOUT = 2VP-P AV = +2, f = 30MHz, VOUT = 2VP-P AV = +2, f = 50MHz, VOUT = 2VP-P AV = +2, f = 100MHz, VOUT = 2VP-P NOTES 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 3 1, 3 1, 3 1, 3 1, 3 1, 3 1 1 1 1 1 1 1 1 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC MIN MAX 750 800 750 750 1000 1000 30 25 65 60 20 20 20 33 -45 -40 -35 -65 -55 -45 UNITS ps ps ps ps ps ps % % % % % % ns ns dBc dBc dBc dBc dBc dBc
TABLE 4. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS Interim Electrical Parameters (Pre Burn-In) Final Electrical Test Parameters Group A Test Requirements Groups C and D Endpoints NOTE: 1. PDA applies to Subgroup 1 only. SUBGROUPS (SEE TABLE 1) 1 1 (Note 1), 2, 3 1, 2, 3 1
Spec Number 3-192
511106-883
HFA1113/883 Die Characteristics
DIE DIMENSIONS: 63 x 44 x 19 mils 1 mils 1600 x 1130 x 483m 25.4m METALLIZATION: Type: Metal 1: AICu(2%)/TiW Thickness: Metal 1: 8kA 0.4kA GLASSIVATION: Type: Nitride Thickness: 4kA 0.5kA WORST CASE CURRENT DENSITY: 2.0 x 105 A/cm2 at 47.5mA TRANSISTOR COUNT: 52 SUBSTRATE POTENTIAL (Powered Up): Floating (Recommend Connection to V-) Type: Metal 2: AICu(2%) Thickness: Metal 2: 16kA 0.8kA
Metallization Mask Layout
HFA1113/883 NC
+IN
V-
VL
-IN
NC
VH
V+
OUT
Spec Number 3-193
511106-883
HFA1113/883 Test Circuit
(Applies to Table 1)
NC VL 0.1 K3 0.1 50
V+ ICC NC K2 -VIN +VIN 0.1 100K (0.01%) 2 1 K1 2 1
+
10
0.1 0.1 510 7 2 DUT + 4 50 K3 0.1 10 0.1 NC K4 IEE 0.1 8 100 100 5 6 1K 510 470pF + x100
Vos = VY
VY 100
0.1 3
VOUT
VZ +IBIAS = 100K VZ
+ HA-5177
0.1
+
NOTE: Terminal Numbers Refer to CerDIP Package All Resistors = 1% () All Capacitors = 10% (F) Unless Otherwise Noted Chip Components Recommended For AV = +1, K1 = Position 1, K2 = Position 1 For AV = +2, K1 = Position 1, K2 = Position 2, -VIN = 0V For AV = -1, K1 = Position 1, K2 = Position 2, +VIN = 0V
V-
VH
Test Waveforms
SIMPLIFIED TEST CIRCUIT FOR LARGE AND SMALL SIGNAL PULSE RESPONSE (Applies to Table 3) AV = +1 or +2 TEST CIRCUIT
V+ 3 + 2 RG V7 6 4 50 50 VOUT 2 VIN RS 50
AV = -1 TEST CIRCUIT
V+ 2 3+ 7 6 4 50 50 VOUT 2
VIN RS 50
V-
NOTE: VS = 5V, RG = 0 for AV = +2, RG = for AV = +1 RF = Internal, RS = 50 RL = 100 For Small and Large Signals Terminal Numbers Refer to CerDIP Package
NOTE: VS = 5V, AV = -1 RF = Internal RS = 50, RL = 100 For Small and Large Signals Terminal Numbers Refer to CerDIP Package
LARGE SIGNAL WAVEFORM
VOUT +2.5V 90% 90% +2.5V VOUT +250mV
SMALL SIGNAL WAVEFORM
90%
90%
+250mV
+SR -2.5V 10% 10%
-SR -2.5V
TR , +OS -250mV 10% 10%
TF , -OS -250mV
Spec Number 3-194
511106-883
HFA1113/883 Burn-In Circuits
HFA1113MJ/883 CERAMIC DIP
1 300 NC 2 D4 VD2 C2 3 4
300
8 7 6 5 R1
D3 V+ C1 D1
+
-
NOTES: R1 = 100, 5% (Per Socket) C1 = C2 = 0.01F (Per Socket) or 0.1F (Per Row) Minimum D1 = D2 = 1N4002 or Equivalent (Per Board) D3 = D4 = 1N4002 or Equivalent (Per Socket) V+ = +5.5V 0.5V V- = -5.5V 0.5V
HFA1113ML/883 CERAMIC LCC
3 4 NC 5 R1 6 7 8 9 10 11 12 13 D4 VD2 C2 300 + 2 1 20 19 300 18 17 D3 V+ C1 R2 D1
-
16 15 14
NOTES: R1 = 1k, 5% (Per Socket) R2 = 100, 5% (Per Socket) C1 = C2 = 0.01F (Per Socket) or 0.1F (Per Row) Minimum D1 = D2 = 1N4002 or Equivalent (Per Board) D3 = D4 = 1N4002 or Equivalent (Per Socket) V+ = +5.5V 0.5V V- = -5.5V 0.5V
Spec Number 3-195
511106-883
HFA1113/883 Ceramic Dual-In-Line Frit Seal Packages (CerDIP)
c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.405 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 10.29 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94
eA
c1 D E e eA eA/2 L Q S1
e
DS
eA/2
c
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 8 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 8 5.08 1.52 105o 0.38 0.76 0.25 0.038
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. 11. Materials: Compliant to MIL-I-38535.
aaa bbb ccc M N
Spec Number 3-196
511106-883
HFA1113/883 Ceramic Leadless Chip Carrier Packages (CLCC)
0.010 S E H S D D3
J20.A
MIL-STD-1835 CQCC1-N20 (C-2) 20 PAD LEADLESS CERAMIC CHIP CARRIER INCHES SYMBOL A A1 B B1
E3 E
MILLIMETERS MIN 1.52 1.27 0.56 MAX 2.54 2.23 0.71 NOTES 6, 7 2, 4 2 2 2 5 5 3 3 3 Rev. 0 4/94
j x 45o
MIN 0.060 0.050 0.022
MAX 0.100 0.088 0.028
B
B2 B3 D D1
0.072 REF 0.006 0.342 0.022 0.358
1.83 REF 0.15 8.69 0.56 9.09
0.200 BSC 0.100 BSC 0.342 0.358 0.358 -
5.08 BSC 2.54 BSC 9.09 9.09
h x 45o 0.010 S E F S A A1 PLANE 2 PLANE 1
D2 D3 E E1 E2 E3
8.69
0.200 BSC 0.100 BSC 0.358 -
5.08 BSC 2.54 BSC 9.09 1.27 BSC 0.38 1.02 REF 0.51 REF 1.14 1.14 1.91 0.08 5 5 20 1.40 1.40 2.41 0.38
-E-
e e1 h
0.050 BSC 0.015 -
0.040 REF 0.020 REF 0.045 0.045 0.075 0.003 5 5 20 0.055 0.055 0.095 0.015
0.007 M E F S H S B1
j L
e
L -HL3
L1 L2 L3 ND NE
-FE1 B3
N NOTES:
E2
L2 B2
L1
e1
D1
D2
1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. 2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol "N" is the maximum number of terminals. Symbols "ND" and "NE" are the number of terminals along the sides of length "D" and "E", respectively. 4. The required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Dimension "A" controls the overall package thickness. The maximum "A" dimension is package height before being solder dipped. 8. Dimensioning and tolerancing per ANSI Y14.5M-1982. 9. Controlling dimension: INCH. 10. Materials: Compliant to MIL-I-38535.
Spec Number 3-197
511106-883
Semiconductor
HFA1113
Output Limiting, Ultra High Speed Programmable Gain Buffer Amplifier
VSUPPLY = 5V, RL = 100, TA = +25oC, Unless Otherwise Specified LARGE SIGNAL PULSE RESPONSE
2.0 AV = +2 1.5 OUTPUT VOLTAGE (V) 5ns/DIV 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 5ns/DIV
DESIGN INFORMATION
August 1999
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Typical Performance Curves
200 AV = +2 150 OUTPUT VOLTAGE (mV) 100 50 0 -50 -100 -150 -200
SMALL SIGNAL PULSE RESPONSE
SMALL SIGNAL PULSE RESPONSE
200 150 OUTPUT VOLTAGE (mV) 100 50 0 -50 -100 -150 -200 5ns/DIV AV = +1 OUTPUT VOLTAGE (V) 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0
LARGE SIGNAL PULSE RESPONSE
AV = +1
5ns/DIV
SMALL SIGNAL PULSE RESPONSE
200 150 OUTPUT VOLTAGE (mV) 100 50 0 -50 -100 -150 -200 5ns/DIV AV = -1 OUTPUT VOLTAGE (V) 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0
LARGE SIGNAL PULSE RESPONSE
AV = -1
5ns/DIV
Spec Number 3-198
511106-883
HFA1113
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Typical Performance Curves
VSUPPLY = 5V, RL = 100, TA = +25oC, Unless Otherwise Specified (Continued) CLAMPED PERFORMANCE (AV = +2, VH = 1V, VL = -1V, 2X Overdrive)
UNCLAMPED PERFORMANCE (AV = +2, VH = 2V, VL = -2V)
AV = +2 IN 0V TO 0.5V IN 0V TO 1V
AV = +2
OUT 0V TO 1V 20ns/DIV
OUT 0V TO 1V 20ns/DIV
FREQUENCY RESPONSE
6 3 GAIN (dB) NORMALIZED 0 PHASE (DEGREES) -3 -6 -9 PHASE -90 AV = +2 AV = -1 AV = +1 -180 -270 -360 GAIN AV = -1 AV = +2 0 VOUT = 200mVP-P AV = +1
FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS
9 6 RL = 50 RL = 100 RL = 1k 0 PHASE RL = 100 RL = 50 RL = 1k -90 PHASE (DEGREES) PHASE (DEGREES) 3 GAIN (dB) 0 GAIN AV = +2, VOUT = 200mVP-P
-180 -270 -360 1000
0.3
1
10 FREQUENCY (MHz)
100
1000
0.3
1
10 100 FREQUENCY (MHz)
FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS
6 3 0 RL = 50 PHASE (DEGREES) -3 GAIN (dB) -6 -9 0 PHASE RL = 100 RL = 50 RL = 1k 0.3 1 10 100 FREQUENCY (MHz) -90 -180 -270 -360 1000 GAIN RL = 100 AV = +1, VOUT = 200mVP-P RL = 1k
FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS
6 3 0 -3 GAIN (dB) -6 -9 RL = 100 180 PHASE 90 0 RL = 50 RL = 1k 0.3 1 10 100 FREQUENCY (MHz) -90 -180 1000 GAIN RL = 100 RL = 50 AV = -1, VOUT = 200mVP-P RL = 1k
Spec Number 3-199
511106-883
HFA1113
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Typical Performance Curves
12 9 6 AV = +2
VSUPPLY = 5V, RL = 100, TA = +25oC, Unless Otherwise Specified (Continued) FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES
6 3 0 GAIN PHASE (DEGREES) -3 GAIN (dB) -6 AV = +1
FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES
1VP-P
GAIN (dB)
0 PHASE
4.0VP-P 2.5VP-P 0 -90 4.0VP-P 2.5VP-P 1VP-P -180 -270 -360 1000
VOUT = 2.5VP-P VOUT = 1VP-P 0 PHASE -90 VOUT = 4VP-P VOUT = 2.5VP-P VOUT = 1VP-P -180 -270 -360 1000
0.3
1
10 100 FREQUENCY (MHz)
0.3
1
10 100 FREQUENCY (MHz)
FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES
6 3 GAIN 0 PHASE (DEGREES) -3 GAIN (dB) -6 PHASE 180 90 VOUT = 4VP-P VOUT = 2.5VP-P VOUT = 1VP-P -180 0.3 1 10 100 FREQUENCY (MHz) 1000 0 -90 VOUT = 1VP-P GAIN (dB) NORMALIZED 15 AV = -1 VOUT = 2.5VP-P VOUT = 4VP-P 12 9 6 3 0 -3 -6 -9 -12 -15 0.3 1
FULL POWER BANDWIDTH
VOUT = 5VP-P
AV = -1 AV = +2 AV = +1
10 FREQUENCY (MHz)
100
1000
-3dB BANDWIDTH vs TEMPERATURE
900 850 800 BANDWIDTH (MHz) 750 700 650 600 AV = +2 550 500 -50 -25 0 +25 +50 +75 +100 +125 TEMPERATURE (oC) AV = +1 AV = -1 GAIN (dB) NORMALIZED 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 -0.05 -0.10 -0.15 1
GAIN FLATNESS
AV = +1
AV = -1
AV = +2
10 FREQUENCY (MHz)
100
Spec Number 3-200
511106-883
PHASE (DEGREES)
3
GAIN
VOUT = 4VP-P
HFA1113
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Typical Performance Curves
4 3 DEVIATION (DEGREES) 2 1 0 -1 -2 -3 -4 -5 -6 0 15 30 45 60 75 90
VSUPPLY = 5V, RL = 100, TA = +25oC, Unless Otherwise Specified (Continued) SETTLING RESPONSE
AV = +2, VOUT = 2V 0.6 AV = -1 SETTLING ERROR (%) 0.4 0.2 0.1 0 -0.1 -0.2 -0.4 -0.6
DEVIATION FROM LINEAR PHASE
AV = +2 AV = +1
105
120
135 150
-2
3
8
13
18
23
28
33
38
43
48
FREQUENCY (MHz)
TIME (ns)
LOW FREQUENCY REVERSE ISOLATION (S12)
-24 -30
HIGH FREQUENCY REVERSE ISOLATION (S12)
180 135 PHASE
-36 -42 GAIN (dB) -48 -54 -60 -66 -72 -78 -84 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (MHz) AV = +2 AV = -1 AV = +2 AV = -1 AV = +1 GAIN (dB) -24 -30 -36 -42 -48 -54 -60 100 190 280 370 GAIN AV = +2 AV = -1
AV = +1 AV = +2
90 45 0 PHASE (DEGREES)
AV = +1 AV = -1
460 550 640 730 FREQUENCY (MHz)
820
910 1000
1dB GAIN COMPRESSION vs FREQUENCY
OUTPUT POWER AT 1dB COMPRESSION (dBm) 20 18 AV = -1 AV = +2 12 10 8 6 4 2 0 100 200 300 FREQUENCY (MHz) 400 500 AV = +1
3rd ORDER INTERMODULATION INTERCEPT vs FREQUENCY
30 2 - TONE
INTERCEPT POINT (dBm)
16 14
AV = -1 20 AV = +2
AV = +1 10
0 100
200
300
400
FREQUENCY (MHz)
Spec Number 3-201
511106-883
HFA1113
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Typical Performance Curves
-20 -30 -40 AV = +2
VSUPPLY = 5V, RL = 100, TA = +25oC, Unless Otherwise Specified (Continued) 3rd HARMONIC DISTORTION vs POUT
-20 -30 -40 DISTORTION (dBc) -50 -60 -70 -80 50MHz -90 -100 100MHz 30MHz AV = +2
2nd HARMONIC DISTORTION vs POUT
DISTORTION (dBc)
-50 -60 100MHz -70 -80 -90 -100 -6 -3 0 3 6 9 12 15 OUTPUT POWER (dBm) 50MHz 30MHz
-6
-3
0
3
6
9
12
15
18
OUTPUT POWER (dBm)
2nd HARMONIC DISTORTION vs POUT
-20 AV = +1 -30 -40 DISTORTION (dBc) -50 -60 -70 -80 -90 -100 -6 -3 0 3 6 9 OUTPUT POWER (dBm) 12 15 100MHz 50MHz 30MHz DISTORTION (dBc) -30 -40 -50 -60 -70 -20
3rd HARMONIC DISTORTION vs POUT
AV = +1
100MHz -80 -90 50MHz 30MHz
-100 -6
-3
0 3 6 9 OUTPUT POWER (dBm)
12
15
2nd HARMONIC DISTORTION vs POUT
-20 AV = -1 -30 -40 DISTORTION (dBc) DISTORTION (dBc) -50 -60 -70 -80 -90 -100 -6 -3 0 3 6 9 OUTPUT POWER (dBm) 12 15 100MHz 50MHz 30MHz -30 -40 -50 -60 -70 -80 -20
3rd HARMONIC DISTORTION vs POUT
AV = -1
50MHz -90 -100 -6 -3 0 3 6 100MHz
30MHz
9
12
15
OUTPUT POWER (dBm)
Spec Number 3-202
511106-883
HFA1113
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Typical Performance Curves
+0.04
VSUPPLY = 5V, RL = 100, TA = +25oC, Unless Otherwise Specified (Continued) OVERSHOOT vs INPUT RISE TIME
60 VOUT = 0.5V 50
INTEGRAL LINEARITY ERROR
PERCENT ERROR (%)
+0.02 OVERSHOOT (%) 40
AV = +1
0
30
20 AV = -1 10 AV = +2 0
-0.02
-0.04 -3.0 -2.0 -1.0 0 +1.0 INPUT VOLTAGE (V) +2.0 +3.0
100
300
500
700
900
1100
1300
INPUT RISE TIME (ps)
OVERSHOOT vs INPUT RISE TIME
60 VOUT = 1V 50 OVERSHOOT (%) OVERSHOOT (%) 50 60
OVERSHOOT vs INPUT RISE TIME
VOUT = 2V
40
AV = +1
40 AV = +1
30
30
20 AV = -1 AV = +2 0 100 300 500 700 900 1100 1300
20 AV = +2
10
10 AV = -1 0 100 300 500 700 900 1100 1300
INPUT RISE TIME (ps)
INPUT RISE TIME (ps)
SUPPLY CURRENT vs SUPPLY VOLTAGE
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 5 6 7 8 9 10 TOTAL SUPPLY VOLTAGE (V+ - V-, V) 25 24 23 SUPPLY CURRENT (mA) 22 21 20 19 18 17 16 15
SUPPLY CURRENT vs TEMPERATURE
SUPPLY CURRENT (mA)
-50
-25
0
+25
+50
+75
+100
+125
TEMPERATURE (oC)
Spec Number 3-203
511106-883
HFA1113
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Typical Performance Curves
3.6 AV = -1 3.5 3.4 OUTPUT VOLTAGE (V) 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 -50 -25 |-VOUT| (RL = 50) |-VOUT| (RL = 100) +VOUT (RL = 50)
VSUPPLY = 5V, RL = 100, TA = +25oC, Unless Otherwise Specified (Continued) INPUT NOISE CHARACTERISTICS
50 130
OUTPUT VOLTAGE vs TEMPERATURE
+VOUT (RL = 100)
30
90
20 eni 10 ini 0
70
50
0 +25 +50 +75 TEMPERATURE (oC)
+100
+125
0.1
1 10 FREQUENCY (kHz)
30 100
NON-LINEARITY NEAR CLAMP VOLTAGE (AV = -1)
20 15 VL = -3V VOUT - (AV * VIN) (mV) 10 5 0 -5 -10 -15 -20 -3 -2 -1 0 AV * VIN (V) 1 2 3 0 0 VH = 1V VH = 2V VH = 3V VL = -2V VL = -1V CLAMP ACCURACY (mV) 350 300
VH CLAMP ACCURACY vs OVERDRIVE
AV = 1 VH = 500mV
250 VH = 1V 200 150 VH = 2V 100 VH = 100mV 50
100
200 300 OVERDRIVE (% OF VH)
400
500
VL CLAMP ACCURACY vs OVERDRIVE
250 AV = 1 VL = 500mV 200 CLAMP ACCURACY (mV) VL = 1V 150 CLAMP ACCURACY (mV) 300 400
VH CLAMP ACCURACY vs OVERDRIVE
AV = +2 VH = 1V
VH = 2V 200 VH = 500mV 100 VH = 100mV
100 VL = 2V 50 VL = 100mV 0 0 100 200 300 400 500
0
0
100
OVERDRIVE (% OF VL)
200 300 OVERDRIVE (% OF VH)
400
500
Spec Number 3-204
511106-883
NOISE CURRENT (pA/Hz)
NOISE VOLTAGE (nV/Hz)
40
110
HFA1113
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Typical Performance Curves
250 AV = +2 CLAMP ACCURACY (mV) 200
VSUPPLY = 5V, RL = 100, TA = +25oC, Unless Otherwise Specified (Continued) OVERDRIVE RECOVERY vs OVERDRIVE
3500
VL CLAMP ACCURACY vs OVERDRIVE
VL = 1V OVERDRIVE RECOVERY TIME (ps) 3000 2500 2000 1500 VL = 500mV 150
VH = 2V
VL = 2V
100
VH = 1V 1000 500 0 VH = 0.5V VH = 0.1V 200 300 400 500
50 VL = 100mV 0 0 100 200 300 OVERDRIVE (% OF VL) 400 500
100
OVERDRIVE LEVEL (% OF CLAMP LEVEL)
CLAMP ACCURACY vs TEMPERATURE
140 130 CLAMP ACCURACY (mV) 120 110 VH 100 90 VL 80 70 60 -75 -25 +25 +50 +75 0 TEMPERATURE (C) +100 +125 +150 AV = -1, VIN = 1.6V VH = 1V, VL = -1V CLAMP BIAS CURRENT (A) 130 120 110 100 90 80 70 60 50 40 30 -50
CLAMP BIAS CURRENT vs TEMPERATURE
VH = 1V, VL = -1V
VL
VH
20 -75
-50
-25
+25 +50 +75 0 TEMPERATURE (C)
+100 +125 +150
VH CLAMP INPUT BANDWIDTH
6 3 0 GAIN (dB) GAIN (dB) -3 -6 -9 -12 VH = 600mVP-P VH = 1.2VP-P VH = 300mVP-P 6 3 0 -3 -6
VL CLAMP INPUT BANDWIDTH
VL = 300mVP-P
VL = 600mVP-P -9 -12 VL = 1.2VP-P
1
10
100 FREQUENCY (MHz)
1000
1
10
100 FREQUENCY (MHz)
1000
Spec Number 3-205
511106-883
HFA1113
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Application Information
Closed Loop Gain Selection The HFA1113 features a novel design which allows the user to select from three closed loop gains, without any external components. The result is a more flexible product, fewer part types in inventory, and more efficient use of board space. This "buffer" operates in closed loop gains of -1, +1, or +2, and gain selection is accomplished via connections to the Inputs. Applying the input signal to +IN and floating -IN selects a gain of +1, while grounding -IN selects a gain of +2. A gain of -1 is obtained by applying the input signal to -IN with +IN grounded. The table below summarizes these connections:
GAIN (ACL) -1 +1 +2 CONNECTIONS +INPUT (PIN 3) GND Input Input -INPUT (PIN 2) Input NC (Floating) GND
Figure 1 details starting points for the selection of this resistor. The points on the curve indicate the RS and CL combinations for the optimum bandwidth, stability, and settling time, but experimental fine tuning is recommended. Picking a point above or to the right of the curve yields an overdamped response, while points below or left of the curve indicate areas of underdamped performance. RS and CL form a low pass network at the output, thus limiting system bandwidth well below the amplifier bandwidth of 850MHz. By decreasing RS as CLincreases (as illustrated in the curves), the maximum bandwidth is obtained without sacrificing stability. Even so, bandwidth does decrease as you move to the right along the curve. For example, at AV = +1, RS = 50, CL = 30pF, the overall bandwidth is limited to 300MHz, and bandwidth drops to 100MHz at AV = +1, RS = 5, CL = 340pF.
PC Board Layout
The frequency response of this amplifier depends greatly on the amount of care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! Attention should be given to decoupling the power supplies. A large value (10F) tantalum in parallel with a small value (0.1F) chip capacitor works well in most cases. Terminated microstrip signal lines are recommended at the input and output of the device. Capacitance directly on the output must be minimized, or isolated as discussed in the next section. For unity gain applications, care must also be taken to minimize the capacitance to ground seen by the amplifier's inverting input. At higher frequencies this capacitance will tend to short the -INPUT to GND, resulting in a closed loop gain which increases with frequency. This will cause excessive high frequency peaking and potentially other problems as well. An example of a good high frequency layout is the Evaluation Board shown in Figure 2.
50 45 40 35 30 25 20 15 10 5 0 RS () AV = +1
AV = +2 0 40 80 120 160 200 240 280 320 LOAD CAPACITANCE (pF) 360 400
FIGURE 1. RECOMMENDED SERIES OUTPUT RESISTOR vs. LOAD CAPACITANCE
Evaluation Board
The performance of the HFA1113 may be evaluated using the HFA11XX Evaluation Board, slightly modified as follows: 1. Remove the 500 feedback resistor (R2), and leave the connection open. 2. A. For AV = +1 evaluation, remove the 500 gain setting resistor (R1), and leave pin 2 floating. B. For AV = +2, replace the 500 gain setting resistor with a 0 resistor to GND. The layout and modified schematic of the board are shown in Figure 2. To order evaluation boards, please contact your local sales office.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly terminated transmission line will degrade the amplifier's phase margin resulting in frequency response peaking and possible oscillations. In most cases, the oscillation can be avoided by placing a resistor (RS) in series with the output prior to the capacitance.
Spec Number 3-206
511106-883
HFA1113
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
TOP LAYOUT
VH 1 +IN OUT V+ VL VGND QP1 +IN VV+ QN1 QN2 ICLAMP Z +1 VH QN5 VH 1 2 3 4 10F 0.1F -5V GND 8 7 50 6 5 GND OUT VL V300 V-IN RF = 300 RG (INTERNAL) (INTERNAL) -IN 0.1F 10F +5V QN3 QP2 QN6 200 QP6 QP5 R1 V+ QP3 QP4
BOTTOM LAYOUT
50K (30K FOR VL)
(AV = +1) or 0 (AV = +2)
R1 50 IN
QN4
VOUT
FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT
FIGURE 3. HFA1113 SIMPLIFIED VH CLAMP CIRCUITRY
Clamp Operation
General The HFA1113 features user programmable output clamps to limit output voltage excursions. Clamping action is obtained by applying voltages to the VH and VL terminals (DIP pins 8 & 5) of the amplifier. VH sets the upper output limit, while VL sets the lower clamp level. If the amplifier tries to drive the output above VH, or below VL, the clamp circuitry limits the output voltage at VH or VL ( the clamp accuracy), respectively. The low input bias currents of the clamp pins allow them to be driven by simple resistive divider circuits, or active elements such as amplifiers or DACs. Clamp Circuitry Figure 3 shows a simplified schematic of the HFA1113 input stage, and the high clamp (VH) circuitry. As with all current feedback amplifiers, there is a unity gain buffer (QX1 - QX2) between the positive and negative inputs. This buffer forces -IN to track +IN, and sets up a slewing current of: (V-IN - VOUT)/RF + V-IN / RG . This current is mirrored onto the high impedance node (Z) by QX3-QX4, where it is converted to a voltage and fed to the output via another unity gain buffer. If no clamping is utilized, the high impedance node may swing within the limits defined by QP4 and QN4. Note that when the output reaches it's quiescent value, the current flowing through -IN is reduced to only that small current (-IBIAS) required to keep the output at the final voltage. Tracing the path from VH to Z illustrates the effect of the clamp voltage on the high impedance node. VH decreases by 2VBE (QN6 and QP6) to set up the base voltage on QP5.
QP5 begins to conduct whenever the high impedance node reaches a voltage equal to QP5's base voltage + 2VBE (QP5 and QN5). Thus, QP5 clamps node Z whenever Z reaches VH. R1 provides a pull-up network to ensure functionality with the clamp inputs floating. A similar description applies to the symmetrical low clamp circuitry controlled by VL. When the output is clamped, the negative input continues to source a slewing current (ICLAMP) in an attempt to force the output to the quiescent voltage defined by the input. QP5 must sink this current while clamping, because the -IN current is always mirrored onto the high impedance node. The clamping current is calculated as: ICLAMP = (V-IN - VOUT CLAMPED) / 300 + V-IN / RG . As an example, a unity gain circuit with VIN = 2V, and VH = 1V, would have ICLAMP = (2V-1V) / 300 + 2V / = 3.33mA (RG = because -IN is floated for unity gain applications). Note that ICC will increase by ICLAMP when the output is clamp limited. Clamp Accuracy The clamped output voltage will not be exactly equal to the voltage applied to VH or VL. Offset errors, mostly due to VBE mismatches, necessitate a clamp accuracy parameter which is found in the device specifications. Clamp accuracy is a function of the clamping conditions. Referring again to Figure 3, it can be seen that one component of clamp accuracy is the VBE mismatch between the QX6 transistors, and the QX5 transistors. If the transistors always ran at the same current level there would be no VBE mismatch, and no contribution to the inaccuracy. The QX6 transistors are biased at a constant current, but as described earlier, the current through QX5 is equivalent to ICLAMP. VBE increases as ICLAMP increases, Spec Number
511106-883
3-207
HFA1113
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
causing the clamped output voltage to increase as well. ICLAMP is a function of the overdrive level (AVCL x VIN - VOUT CLAMPED), so clamp accuracy degrades as the overdrive increases. As an example, the specified accuracy of 100mV for a 1.6X overdrive degrades to 240mV for a 3X overdrive. Consideration must also be given to the fact that the clamp voltages have an affect on amplifier linearity. The "Nonlinearity Near Clamp Voltage" curve in the data sheet illustrates the impact of several clamp levels on linearity. Clamp Range Unlike some competitor devices, both VH and VL have usable ranges that cross 0V. While VH must be more positive than VL, both may be positive or negative, within the range restrictions indicated in the specifications. For example, the HFA1113 could be limited to ECL output levels by setting VH = -0.8V and VL = -1.8V. VH and VL may be connected to the same voltage (GND for instance) but the result won't be a DC output voltage from an AC input signal. A 150 - 200mV AC signal will still be present at the output.
Recovery from Overdrive The output voltage remains at the clamp level as long as the overdrive condition remains. When the input voltage drops below the overdrive level (VCLAMP / AVCL) the amplifier will return to linear operation. A time delay, known as the Overdrive Recovery Time, is required for this resumption of linear operation. The plots of "Unclamped Performance" and "Clamped Performance" highlight the HFA1113's subnanosecond recovery time. The difference between the unclamped and clamped propagation delays is the overdrive recovery time. The appropriate propagation delays are 8.0ns for the unclamped pulse, and 8.8ns for the clamped (2X overdrive) pulse yielding an overdrive recovery time of 800ps. The measurement uses the 90% point of the output transition to ensure that linear operation has resumed. Note: The propagation delay illustrated is dominated by the fixturing. The delta shown is accurate, but the true HFA1113 propagation delay is 500ps.
TYPICAL PERFORMANCE CHARACTERISTICS Device Characterized at: VSUPPLY = 5V, AV = +2V/V, RL = 100, Unless Otherwise Specified. PARAMETERS Output Offset Voltage Average Offset Voltage Drift +Input Current +Input Resistance -Input Resistance +Input Noise Voltage * +Input Noise Current * Input Common Mode Range Input Capacitance Gain Gain DC Non-Linearity * Output Voltage * AV = +1, VIN = 2V AV = +2, VIN = 1V VOUT = 2V Full Scale AV = -1, RL = 100 AV = -1, RL = 100 Output Current * AV = -1, RL = 50 AV = -1, RL = 50 DC Closed Loop Output Resistance Quiescent Supply Current * -3dB Bandwidth * RL = Open AV = -1, VOUT = 200mVP-P AV = +1, VOUT = 200mVP-P AV = +2, VOUT = 200mVP-P +25oC f = 100kHz f = 100kHz CONDITIONS AV = +1, VCM = 0V Versus Temperature AV = +1, VCM = 0V AV = +1, VCM = 2V TEMPERATURE +25oC Full +25oC +25oC +25oC +25oC +25oC Full +25oC +25oC +25oC +25oC +25oC Full to +125oC 0oC TYPICAL 8 10 25 50 300 9 37 2.8 2.2 0.99 1.98 0.02 3.3 3.0 60 50 0.3 24 800 850 550 UNITS mV V/oC A k nV/Hz pA/Hz V pF V/V V/V % V V mA mA mA MHz MHz MHz
-55oC
to
+25oC Full +25oC +25oC +25oC
Spec Number 3-208
511106-883
HFA1113
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
TYPICAL PERFORMANCE CHARACTERISTICS (Continued) Device Characterized at: VSUPPLY = 5V, AV = +2V/V, RL = 100, Unless Otherwise Specified. PARAMETERS Slew Rate CONDITIONS AV = -1, VOUT = 5VP-P AV = +1, VOUT = 5VP-P AV = +2, VOUT = 5VP-P Full Power Bandwidth (Note 1) AV = -1, VOUT = 5VP-P AV = +1, VOUT = 5VP-P AV = +2, VOUT = 5VP-P Gain Flatness (Note 1) To 30MHz, AV = -1 To 30MHz, AV = +1 To 30MHz, AV = +2 Gain Flatness (Note 1) To 50MHz, AV = -1 To 50MHz, AV = +1 To 50MHz, AV = +2 Gain Flatness (Note 1) To 100MHz, AV = -1 To 100MHz, AV = +2 Linear Phase Deviation (Note 1) To 100MHz, AV = -1 To 100MHz, AV = +1 To 100MHz, AV = +2 2nd Harmonic Distortion (Note 1) 30MHz, AV = -1, VOUT = 2VP-P 30MHz, AV = +1, VOUT = 2VP-P 30MHz, AV = +2, VOUT = 2VP-P 3rd Harmonic Distortion (Note 1) 30MHz, AV = -1, VOUT = 2VP-P 30MHz, AV = +1, VOUT = 2VP-P 30MHz, AV = +2, VOUT = 2VP-P 2nd Harmonic Distortion (Note 1) 50MHz, AV = -1, VOUT = 2VP-P 50MHz, AV = +1, VOUT = 2VP-P 50MHz, AV = +2, VOUT = 2VP-P 3rd Harmonic Distortion (Note 1) 50MHz, AV = -1, VOUT = 2VP-P 50MHz, AV = +1, VOUT = 2VP-P 50MHz, AV = +2, VOUT = 2VP-P 2nd Harmonic Distortion (Note 1) 100MHz, AV = -1, VOUT = 2VP-P 100MHz, AV = +1, VOUT = 2VP-P 100MHz, AV = +2, VOUT = 2VP-P 3rd Harmonic Distortion (Note 1) 100MHz, AV = -1, VOUT = 2VP-P 100MHz, AV = +1, VOUT = 2VP-P 100MHz, AV = +2, VOUT = 2VP-P TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC TYPICAL 2400 1500 1900 300 150 220 0.02 0.10 0.015 0.05 0.20 0.036 0.10 0.07 0.13 0.83 0.05 -52 -57 -52 -71 -73 -72 -47 -53 -47 -63 -68 -65 -41 -50 -42 -55 -49 -62 UNITS V/s V/s V/s MHz MHz MHz dB dB dB dB dB dB dB dB Degrees Degrees Degrees dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
Spec Number 3-209
511106-883
HFA1113
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
TYPICAL PERFORMANCE CHARACTERISTICS (Continued) Device Characterized at: VSUPPLY = 5V, AV = +2V/V, RL = 100, Unless Otherwise Specified. PARAMETERS 3rd Order Intercept (Note 1) 100MHz 300MHz 1dB Compression (Note 1) 100MHz 300MHz Reverse Isolation (S12) (Note 1) 40MHz 100MHz 600MHz Rise and Fall Time AV = -1, VOUT = 0.5VP-P AV = +1, VOUT = 0.5VP-P AV = +2, VOUT = 0.5VP-P Overshoot (Note 1) AV = -1, VOUT = 0.5VP-P AV = +1, VOUT = 0.5VP-P AV = +2, VOUT = 0.5VP-P Settling Time (Note 1) AV = +2, to 0.1%, VOUT = 2V to 0V AV = +2, to 0.05%, VOUT = 2V to 0V AV = +2, to 0.02%, VOUT = 2V to 0V Differential Gain Differential Phase Overdrive Recovery Time, (2X Overdrive) Clamp Accuracy Clamped Overshoot Negative Clamp Range (VL) Positive Clamp Range (VH) Clamp Input Bias Current Clamp Input Bandwidth NOTE: 1. See Typical Performance Curves for more information. VH = +1V, VL = -1V VIN = 100mV, VH or VL = 100mVP-P AV = +2, RL = 150, NTSC AV = +2, RL = 150, NTSC VIN = 1V, VH = +1V, VL = -1V AV = -1, VIN = 1.6V, VH = +1V, VL = -1V VIN = 1V, VH = +1V, VL = -1V, Input tR / tF = 2ns CONDITIONS TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC TYPICAL 28 13 19 12 -70 -60 -32 500 480 700 12 45 6 13 20 36 0.02 0.04 0.75 100 7 -5.0 to +2.0 -2.0 to +5.0 50 500 UNITS dBm dBm dBm dBm dB dB dB ps ps ps % % % ns ns ns % Degrees ns mV % V V A MHz
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Spec Number 3-210
511106-883

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